1. Field of the Invention
The present invention relates to a method of forming elements on a semiconductor substrate, thinning the substrate, separating the elements, and fabricating the elements into semiconductor devices. In particular, the present invention relates to a method of efficiently mass-producing Gunn diodes.
2. Description of Background Information
Gunn diodes usually employ one of IHS (Integral Heat Sink) and PHS (Plated Heat Sink) structures that are effective for reducing thermal resistance and for mass production.
FIGS. 1(A) to 1(F) show a method of fabricating the Gunn diodes of IHS structure. This method has been disclosed by N. Apsley et al. in "Indium Phosphide Millimeter Wave Transferred Electron Oscillators" in Inst. Phys. Conf. Ser. No. 56, p. 483, 1981, the disclosure of which is hereby incorporated by reference in its entirety.
In FIG. 1(A), a semiconductor substrate 91 is made from Indium Phosphide (InP). An epitaxial layer 92 of InP is grown to a thickness of several micrometers on a first principal plane of the substrate 91. The epitaxial layer 92 is composed of an active layer and high-concentration impurity layers on each side of the active layer. A first ohmic electrode 93 of Ge--Au--Ni is formed over the epitaxial layer 92. The ohmic electrode 93 and epitaxial layer 92 are etched to form a grid recess 94.
In FIG. 1(B), a thick Ag plated layer 95 is formed to a thickness of about 60 micrometers over the first ohmic electrode 93 and grid recess 94. On top of the plated layer 95, a thin Ni--Ag layer 95' is formed to improve bonding characteristics.
In FIG. 1(C), the plated layer 95 is supported, and a second principal plane of the substrate 91 is ground until the grid recess 94 is exposed.
In FIG. 1(D), a second ohmic electrode 96 is formed over the ground plane. An Au plated layer 97 is formed to a thickness of about 10 micrometers at the center of each square of the grid recess 94.
In FIG. 1(E), the second ohmic electrode 96 around the Au plated layer 97 is removed by chemical etching. The exposed InP area is removed by photoetching, to form mesa structures 98 having vertical side faces on the plated layer 95.
In FIG. 1(F), the plated layer 95 is diced to form individual elements 99, which are packaged into semiconductor devices.
The plated layer 95 of the IHS or PHS structure is as thick and large as the element, so that the dicing process and the processes following it cause a decrease in productivity and yield. Namely, the IHS or PHS structure is improper for mass production.
If the mesa elements are closely arranged at intervals of the width of each element, it will be very difficult to dice them into individual elements.